1. Field of the Invention
This invention relates generally to the data processing apparatus and, more particularly, to the specialized high performance processor units generally referred to as digital signal processing units. The invention relates specifically to address modification by the direct memory access controller.
2. Background of the Invention
Digital signal processing units have been developed as specialized data processing units. These units are optimized to perform routine, albeit complex, operations with great efficiency. For many applications, the computations need to done in as close to real time as possible. In addition, many of the functions that would be performed by the central processing unit of a general purpose processing unit are eliminated or the functions performed outside of the core processing unit.
Referring to FIG. 1, a digital signal processing unit 1 having two digital signal processors, according to the prior art, is shown. A first digital signal processor 10 includes a core processing unit 12 (frequently referred to as a processing core), a direct memory access unit 14, a memory unit or memory units 16, and a serial port or serial ports 18. The memory unit 16 stores the signal groups that are to be processed or that assist in the processing of the signal groups by the core processing unit 12. The core processing unit 12 performs the bulk of the processing of signal groups in the memory unit. The direct memory access unit 14 is coupled to the core processing unit 12 and to memory unit 16 and mediates the signal group exchange therebetween. The serial port 18 exchanges signal groups with processing components external to the digital signal processing unit 1. The core processing unit 12 is coupled to the serial port 18 and to the memory unit 16 and controls the exchange of signal groups between these components.
The digital signal processor is typically designed and implemented to have limited functionality, but functions that must be repeated and performed rapidly. The fast Fourier transform (FFT) calculation and the Viterbi algorithm decoding are two examples where digital signal processors have been utilized with great advantage. To insure that the digital signal processors operate with high efficiency, the core processing is generally optimized for the performance of the limited functionality. Part of the optimization process involves the off-loading, to the extent possible, any processing not directed toward the optimized function(s). The exchange of signal groups involving the core processing unit 12 and the memory unit 16 has been assigned to the direct memory access unit.
More recently, the direct memory access controller has been implemented to control the exchange of data groups between the serial port and the memory unit. This embodiment of a digital signal processor is described in the Patent Application entitled APPARATUS AND METHOD FOR THE EXCHANGE OFSIGNAL GROUPS BETWEEN A PLURALITY COMPONENTS AND A DIRECT MEMORY ACCESS CONTROLLER IN A DIGITAL SIGNAL PROCESSSOR cited above. Referring to FIG. 2, the digital signal processor 10, have a core processing unit 12, a direct memory access controller, a memory unit 16, and a serial port 18, the same components as in the prior art digital signal processors shown in FIG. 1. The difference between the embodiments in FIG. 1 and FIG. 2 is as follows. In FIG. 1, the direct memory access controller 14, control the exchange of signal groups between the memory unit 16, and the core processing unit 12. In FIG. 2, the direct memory access controller 24 controls not only the exchange of signal groups between the memory unit 16, and the core processing unit 12, but also controls the exchange of signal groups between the memory unit 16 and the serial port 18. With this implementation, the core processing unit 12 is relieved of further processing responsibilities, as compared to the implementation shown in FIG. 1 For example, the memory unit 16 to serial port 18 exchange of data signals can have a variety of addressing modes such as a frame mode, a circular buffer memory mode and a sorting mode. The core processing unit 12 is relieved of the responsibility for implementing the addressing modes. Thus, the core processing unit 12 can be further optimized for specific processing operations. The direct memory access controller can be analogized to a plurality of controllable switches. The switches provide controllable channels for the transfer of signals between components. (In the preferred embodiment of the digital signal processors, typically two memory units and two serial ports are present. Consequently, a larger number of channels can be used. In the preferred embodiment, six channels are available in the direct memory access controller 24.)
As the direct memory access controller 24 has been assigned greater responsibilities in the controlling the transfer of signal groups, the computational requirements for the component have been similarly expanded. In particular, not only is the generation of source and destination addresses required, but the several addressing conventions, mentioned above, must implemented by the direct memory access controller 24. Specifically, the addressing apparatus must be able to implement both a frame mode and a circular buffer mode. (In the circular buffer mode, a group of consecutive locations in the memory unit 16 are designated as the circular buffer memory and signal groups are stored therein or extracted therefrom. After the last location in the circular buffer memory is addressed, the addresses are xe2x80x9cwrapped aroundxe2x80x9d to the beginning of the buffer memory. The wrap-around of the addresses in the circular buffer can be positive or negative.) In addition, the addressing apparatus must be capable of operating in a sorting mode. The sorting mode refers to the time-division multiplexed groups of signal groups such as the T1 protocol (U.S.) or the E1 protocol (Europe). In this addressing mode, the signal groups from a multiplicity of blocks of signal groups are xe2x80x9csortedxe2x80x9d into frames of signal groups, i.e., each frame including related signal groups. In addition, because performance is key in digital signal processors, the new address must be formulated rapidly.
A need has therefore been felt for apparatus and an associated method for modifying/generating an address in a direct memory access controller having the feature that a multiplicity of address modes can be accommodated by the apparatus and associated method. It would be a further feature of the present invention that the modification or creation of the address would take place in a time period that would not impact the performance of the digital signal processing system. It would be a more specific feature of the apparatus and method that a sorting mode would be provided for the time-division multiplexed signal groups. It is a further specific feature of the present invention to provide for the address modification or generation involving a circular address buffer.
The aforementioned and other features are accomplished, according to the present invention, by providing an address modification apparatus that can process a multiplicity of addressing modes using the same apparatus. The apparatus determines the proper addressing mode while simultaneously selecting a offset that will be involved in determining the new address from a former address or a base address. The address base and previous index are determined. A plurality of simultaneous calculations are performed that include possible circular buffer memory address results. The correct new index is selected from the determination of the addressing mode and characteristics of the previous address. The new index is combined with the base address to form the new address. The new address is forwarded to the addressing apparatus and is used to determine the next address. To increase the speed, the results of one computation are immediately coupled to apparatus performing a subsequent computation.